View 71T75602100PFI8_8667058.PDF datasheet online --- IC-ON-LINE

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april 2012 dsc-5313/10 1 ?2012 integrated device technology, inc. a 0 -a 19 address inputs input synchronous ce 1 , ce 2 , ce 2 chip enables input synchronous oe output enable input asynchronous r/ w read/write signal input synchronous cen clock enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 individual byte write selects input synchronous clk clock input n/a adv/ ld advance burst address / load new address input synchronous lbo linear / interleaved burst order input static tms test mode select input n/a tdi test data input input n/a tck test clock input n/a tdo test data input output n/a trst jtag reset (optional) input asynchronous zz sleep mode input synchronous i/o 0 -i/o 31 , i/o p1 -i/o p4 data input / output i/o synchronous v dd , v ddq core power, i/o power supply static v ss ground supply static 5 313 tbl 01 pin description summary features ? 512k x 36, 1m x 18 memory configurations ? supports high performance system speed - 200 mhz (3.2 ns clock-to-data access) ? zbt tm feature - no dead cycles between write and read cycles ? internally synchronized output buffer enable eliminates the need to control oe ? single r/ w (read/write) control pin ? positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ? 4-word burst capability (interleaved or linear) ? individual byte write ( bw 1 - bw 4 ) control (may tie active) ? three chip enables for simple depth expansion ? 2.5v power supply (5%) ? 2.5v i/o supply (v ddq ) ? power down controlled by zz input ? boundary scan jtag interface (ieee 1149.1 compliant) ? packaged in a jedec standard 100-pin plastic thin quad flatpack (tqfp), 119 ball grid array (bga) idt71t75602 idt71t75802 512k x 36, 1m x 18 2.5v synchronous zbt? srams 2.5v i/o, burst counter pipelined outputs description the idt71t75602/802 are 2.5v high-speed 18,874,368-bit (18 megabit) synchronous srams. they are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. thus, they have been given the name zbt tm , or zero bus turnaround. address and control signals are applied to the sram during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. the idt71t75602/802 contain data i/o, address and control signal registers. output enable is the only asynchronous signal and can be used to disable the outputs at any given time. a clock enable cen pin allows operation of the idt71t75602/802 to be suspended as long as necessary. all synchronous inputs are ignored when ( cen ) is high and the internal device registers will hold their previous values. there are three chip enable pins ( ce 1 , ce 2 , ce 2 ) that allow the user to deselect the device when desired. if any one of these three is not asserted when adv/ ld is low, no new memory operation can be initiated. however, any pending data transfers (reads or writes) will be completed.
6.42 2 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk. symbol pin function i/o active description a 0 -a 19 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk, adv/ ld low, cen low, and true chip enables. adv/ ld advance / load i n/a adv/ ld is a sync hronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. when adv/ ld is low with the chip deselected, any burst in progress is terminated. when adv/ ld is sampled high then the internal burst counter is advanced for any burst that was in progress. the external addresses are ignored when adv/ ld is sampled high. r/ w read / write i n/a r/ w signal is a synchronous input that identifies whether the current load cycle initiated is a read or write access to the memory array. the data bus activity for the current cycle takes place two clock cycles later. cen clock enable i low synchronous clock enable input. when cen is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. the effect of cen sampled high on the device outputs is as if the low to high clock transition did not occur. for normal operation, cen must be sampled low at rising edge of clock. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. each 9-bit byte has its own active low byte write enable. on load write cycles (when r/ w and adv/ ld are sampled low) the appropriate byte write signal ( bw 1 - bw 4 ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when r/ w is sampled high. the appropriate byte(s) of data are written into the device two cycles later. bw 1 - bw 4 can all be tied low if always doing write to the entire 36-bit word. ce 1 , ce 2 chip enables i low synchronous active low chip enable. ce 1 and ce 2 are used with ce 2 to enable the idt71t75602/802 ( ce 1 or ce 2 sampled high or ce 2 sampled low) and adv/ ld low at the rising edge of clock, initiates a deselect cycle. the zbt tm has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. ce 2 chip enable i high synchronous active high chip enable. ce 2 is used with ce 1 and ce 2 to enable the chip. ce 2 has inverted polarity but otherwise identical to ce 1 and ce 2 . clk clock i n/a this is the clock input to the idt71t75602/802. except for oe , all timing references for the device are made with respect to the rising edge of clk. i/o 0 -i/o 31 i/o p1 -i/o p4 data input/output i/o n/a synchronous data input/output (i/o) pins. both the data input path and data output path are reg istered a nd triggered by the rising edge of clk. lbo linear burst order i low burst order selection input. when lbo is high the interleaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo is a static input and it must not change during device operation. oe output enable i low asynchronous output enable . oe must be low to read data from the 71t75602/802. whe n oe is high the i/o pins are in a high-imped ance state. oe does not need to be actively controlled for read and write cycles. in normal operation, oe can be tied low. tms test mode select i n/a gives input command for tap controller. sampled on rising edge of tdk. this pin has an internal pullup. tdi test data input i n/a serial input of registers placed between tdi and tdo. sampled on ris ing edge of tck. this pin has an internal pullup. tck test clo ck i n/a clock input of tap controller. each tap event is clocked. test inputs are captured on rising edge of tck, while test outputs are driven from the falling edge of tck. this pin has an internal pullup. tdo test data output o n/a serial output of registers placed between tdi and tdo. this output is active depending on the state of the tap controller. trst jtag reset (optional) ilow optional asynchronous jtag reset. can be used to reset the tap controller, but not required. jtag reset occurs automatically at power up and also resets using tms and tck per ieee 1149.1. if not used trst can be left floating. this pin has an internal pullup. only available in bga package. zz sleep mode i high synchro nous sleep mode input. zz high will gate the clk internally and power down the idt71t75602/802 to its lowest power consumption level. data retention is guaranteed in sleep mode. this pin has an internal pulldown. v dd power supply n/a n/a 2.5v core power supply. v ddq power supply n/a n/a 2.5v i/o supply. v ss ground n/a n/a ground. 5313 tbl 02 description (cont.) the data bus will tri-state two cycles after the chip is deselected or a write is initiated. the idt71t75602/802 have an on-chip burst counter. in the burst mode, the idt71t75602/802 can provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the lbo input pin. the lbo pin selects between linear and interleaved burst sequence. the adv/ ld signal is used to load a new external address (adv/ ld = low) or increment the internal burst counter (adv/ ld = high). the idt71t75602/802 srams utilize a high-performance 2.5v cmos process, and are packaged in a jedec standard 14mm x 20mm 100pin thin plastic quad flatpack (tqfp) as well as a 119 ball grid array (bga).
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 3 functional block diagram clk dq dq dq address a [0:18] control logic address control di do input register 5313 drw 01 clock data i/o [0:31], i/o p[1:4] d q clk output register mux sel gate o e c e 1, ce2, c e 2 r/ w c e n adv/ l d b w x l b o 512kx36 bit memory array jtag tms tdi tck tdo t r s t (optional) clk dq dq dq address a [0:19] control logic address control di do input register 5313 drw 01b clock data i/o [0:15], i/o p[1:2] d q clk output register mux sel gate o e c e 1, ce2, c e 2 r/ w c e n adv/ l d b w x l b o 1mx18 bit memory array jtag tms tdi tck tdo t r s t (optional)
6.42 4 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges recommended operating temperature and supply voltage pin configuration ? 512k x 36 notes: 1. pins 14, 16, and 66 do not have to be connected directly to v dd as long as the input voltage is v ih . 2. pins 38, 39 and 43 will be pulled internally to v dd if not actively driven. to disable the tap controller without interfering with normal operation, several settings are possible. pins 38, 39 and 43 could be tied to v dd or v ss and pin 42 should be left unconnected. or all jtag inputs (tms, tdi and tck) pins 38, 39 and 43 could be left unconnected ?nc? and the jtag circuit will remain disabled from power up. 3. pin 43 is reserved for the 36m address. jtag is not offered in the 100-pin tqfp package for the 36m zbt device. top view 100 tqfp recommended dc operating conditions note: 1. v il (min.) = ?0.8v for pulse width less than t cyc /2, once per cycle. symbol parameter min. typ. max. unit v dd core supply voltage 2.375 2.5 2.625 v v ddq i/o supply voltage 2.375 2.5 2.625 v v ss ground 000v v ih input high voltage - inputs 1.7 ____ v dd +0.3 v v ih input high voltage - i/o 1.7 ____ v ddq +0.3 v v il input low voltage -0.3 (1) ____ 0.7 v 5313 tbl 03 grade ambient temperature (1) v ss v dd v ddq commercial 0 c to +70 c ov 2.5v 5% 2.5v 5% industrial -40 c to +85 c ov 2.5v 5% 2.5v 5% 5313 tbl 05 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 ce 1 ce 2 bw 4 bw 3 bw 2 bw 1 ce 2 v dd v ss clk r/ w cen oe adv/ ld a 18 a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc / tck (2,3) nc / tdo (2) nc / tdi (2) nc / tms (2) lbo a 14 a 13 a 12 a 11 a 10 v dd v ss a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 5313 drw 02 v dd (1) i/o 15 i/o p3 v dd (1) i/o p4 a 15 a 16 i/o p1 v dd (1) i/o p2 zz a 17 note: 1. during production testing, the case temperature equals the ambient temperature.
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 5 absolute maximum ratings (1) pin configuration ? 1mx 18 100-pin tqfp capacitance (t a = +25c, f = 1.0mhz) notes: 1. pins 14, 16, and 66 do not have to be connected directly to v dd as long as the input voltage is v ih . 2. pins 38, 39 and 43 will be pulled internally to v dd if not actively driven. to disable the tap controller without interfering with normal operation, several settings are possible. pins 38, 39 and 43 could be tied to v dd or v ss and pin 42 should be left unconnected. or all jtag inputs (tms, tdi and tck) pins 38, 39 and 43 could be left unconnected ?nc? and the jtag circuit will remain disabled from power up. 3. pin 43 is reserved for the 36m address. jtag is not offered in the 100-pin tqfp package for the 36m zbt device. top view 100 tqfp notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. during production testing, the case temperature equals t a . note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol rating commercial industrial unit v te rm (2) terminal voltage with respect to gnd -0.5 to +3.6 -0.5 to +3.6 v v te rm (3,6) terminal voltage with respect to gnd -0.5 to v dd -0.5 to v dd v v te rm (4,6) terminal voltage with respect to gnd -0.5 to v dd +0.5 -0.5 to v dd +0.5 v v te rm (5,6) terminal voltage with respect to gnd -0.5 to v ddq +0.5 -0.5 to v ddq +0.5 v t a (7) operating ambient temperature 0 to +70 -40 to +85 o c t bias temperature under bias -55 to +125 -55 to +125 o c t stg storage temperature -55 to +125 -55 to +125 o c p t power dissipation 2.0 2.0 w i out dc output current 50 50 ma 5313 tbl 06 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 5313 tbl 07 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 ce 1 ce 2 nc nc bw 2 bw 1 ce 2 v dd v ss clk r/ w cen oe adv/ ld a 19 a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 lbo a 15 a 14 a 13 a 12 a 11 v dd v ss a 0 a 1 a 2 a 3 a 4 a 5 nc nc v ddq v ss nc i/o p2 i/o 15 i/o 14 v ss v ddq i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 v ddq v ss i/o 9 i/o 8 nc nc v ss v ddq nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc v ddq v ss nc i/o p1 i/o 7 i/o 6 v ss v ddq i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 v ddq v ss i/o 1 i/o 0 nc nc v ss v ddq nc nc 5313 drw 02a v dd (1) nc nc v dd (1) nc a 16 a 17 nc v dd (1) a 10 zz a 18 , nc / tck (2,3) nc / tdo (2) nc / tdi (2) nc / tms (2) symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 7 pf 5313 tbl 07a symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 7 pf 5313 tb l 07b 165 fbga capacitance (t a = +25c, f = 1.0mhz) 119 bga capacitance (t a = +25c, f = 1.0mhz)
6.42 6 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges notes: 1. j3, r5, and j5 do not have to be directly connected to v dd as long as the input voltage is v ih . 2. u2, u3, u4 and u6 will be pulled internally to v dd if not actively driven. to disable the tap controller without interfering with normal operation, several settings are possible. u2, u3, u4 and u6 could be tied to vdd or vss and u5 should be left unconnected. or all jtag inputs(tms, tdi, and tck and trst ) u2, u3, u4 and u6 could be left unconnected ?nc? and the jtag circuit will remain disabled from power up. 3. the 36m address will be ball t6 (for the 512k x 36 device) and ball t4 (for the 1m x 18 device). 4. trst is offered as an optional jtag reset if required in the application. if not needed, can be left floating and will internally be pulled to v dd . top view pin configuration ? 1m x 18, 119 bga (1,2) top view pin configuration ? 512k x 36, 119 bga (1,2) 12345 6 7 av ddq a 6 a 4 a 18 a 8 a 16 v ddq bncce 2 a 3 adv/ ld a 9 ce 2 nc cnca 7 a 2 v dd a 12 a 15 nc di/o 16 i/o p3 v ss nc v ss i/o p2 i/o 15 ei/o 17 i/o 18 v ss ce 1 v ss i/o 13 i/o 14 fv ddq i/o 19 v ss oe v ss i/o 12 v ddq gi/o 20 i/o 21 bw 3 a 17 bw 2 i/o 11 i/o 10 hi/o 22 i/o 23 v ss r/ w v ss i/o 9 i/o 8 jv ddq v dd v dd (1) v dd v dd (1) v dd v ddq ki/o 24 i/o 26 v ss clk v ss i/o 6 i/o 7 li/o 25 i/o 27 bw 4 nc bw 1 i/o 4 i/o 5 mv ddq i/o 28 v ss cen v ss i/o 3 v ddq ni/o 29 i/o 30 v ss a 1 v ss i/o 2 i/o 1 pi/o 31 i/o p4 v ss a 0 v ss i/o p1 i/o 0 rnca 5 lbo v dd v dd (1) a 13 nc tncnca 10 a 11 a 14 nc (3) zz uv ddq nc/tms (2) nc/tdi (2) nc/tck (2) nc/tdo (2) nc/ trst (2 , 4) v ddq 5313 tbl 25 1234567 av ddq a 6 a 4 a 19 a 8 a 16 v ddq bncce 2 a 3 adv/ ld a 9 ce 2 nc cnca 7 a 2 v dd a 13 a 17 nc di/o 8 nc v ss nc v ss i/o p1 nc enci/o 9 v ss ce 1 v ss nc i/o 7 fv ddq nc v ss oe v ss i/o 6 v ddq gnci/o 10 bw 2 a 18 v ss nc i/o 5 hi/o 11 nc v ss r/ w v ss i/o 4 nc jv ddq v dd v dd (1) v dd v dd (1) v dd v ddq knci/o 12 v ss clk v ss nc i/o 3 li/o 13 nc v ss nc bw 1 i/o 2 nc mv ddq i/o 14 v ss cen v ss nc v ddq ni/o 15 nc v ss a 1 v ss i/o 1 nc pnci/o p2 v ss a 0 v ss nc i/o 0 rnca 5 lbo v dd v dd (1) a 12 nc tnca 10 a 15 nc (3) a 14 a 11 zz uv ddq nc/tms (2) nc/tdi (2) nc/tck (2) nc/tdo (2) nc /trst (2 , 4) v ddq 53 13 tb l 2 5a
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 7 synchronous truth table (1) partial truth table for writes (1) notes: 1. l = v il , h = v ih , x = don?t care. 2. when adv/ ld signal is sampled high, the internal burst counter is incremented. the r/ w signal is ignored when the counter is advanced. therefore the nature of the burst cycle (read or write) is determined by the status of the r/ w signal when the first address is loaded at the beginning of the burst cycle. 3. deselect cycle is initiated when either ( ce 1 , or ce 2 is sampled high or ce 2 is sampled low) and adv/ ld is sampled low at rising edge of clock. the data bus will tri-state two cycles after deselect is initiated. 4. when cen is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. the state of all th e internal registers and the i/os remains unchanged. 5. to select the chip requires ce 1 = l, ce 2 = l, ce 2 = h on these chip enables. chip is deselected if any one of the chip enables is false. 6. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. 7. q - data read from the device, d - data written to the device. notes: 1. l = v il , h = v ih , x = don?t care. 2. multiple bytes may be selected during the same cycle. 3. n/a for x18 configuration. cen r/ w chip (5) enable adv/ ld bw x address used previous cycle current cycle i/o (2 cycles later) l l select l valid external x load write d (7) l h select l x external x load read q (7 ) l x x h valid internal load write / burst write burst write (advance burst counter) (2 ) d (7) l x x h x internal load read / burst read burst read (advance burst counter) (2 ) q (7 ) l x deselect l x x x deselect or stop (3 ) hiz l x x h x x deselect / noop noop hiz h x x x x x x suspend (4 ) previous value 5 313 tbl 08 operation r/ w bw 1 bw 2 bw 3 (3) bw 4 (3) read h x x x x write all bytes lllll write byte 1 (i/o[0:7], i/o p1 ) (2 ) l l hhh write byte 2 (i/o[8:15], i/o p2 ) (2) lhlhh write byte 3 (i/o[16:23], i/o p3 ) (2,3) lhhlh write byte 4 (i/o[24:31], i/o p4 ) (2,3) lhhhl no write lhhhh 53 13 tbl 09
6.42 8 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges linear burst sequence table ( lbo =v ss ) interleaved burst sequence table ( lbo =v dd ) functional timing diagram (1) notes: 1. this assumes cen , ce 1 , ce 2 , ce 2 are all true. 2. all address, control and data_in are only required to meet set-up and hold time with respect to the rising edge of clock. da ta_out is valid after a clock-to-data delay from the rising edge of clock. note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11100100 5313 tbl 10 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11000110 5313 tbl 11 n+29 a29 c29 d/q27 address (2) (a 0 - a 18 ) control (2) (r/ w , adv/ ld , bw x) data (2) i/o [0:31] , i/o p [1:4] cycle clock n+30 a30 c30 d/q28 n+31 a31 c31 d/q29 n+32 a32 c32 d/q30 n+33 a33 c33 d/q31 n+34 a34 c34 d/q32 n+35 a35 c35 d/q33 n+36 a36 c36 d/q34 n+37 a37 c37 d/q35 5313drw 03
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 9 notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. read operation (1) device operation - showing mixed load, burst, deselect and noop cycles (2) notes: 1. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 2. h = high; l = low; x = don?t care; z = high impedance. cycle address r/ w adv/ ld ce (1) cen bw x oe i/o comments na 0 hl llxxxload read n+1 x x h x l x x x burst read n+2 a 1 hl llxlq 0 load read n+3 x x l h l x l q 0+1 deselect or stop n+4 x x h xlxlq 1 noop n+5 a 2 hl llxxzload read n+6 x x h x l x x z burst read n+7 x x l h l x l q 2 deselect or stop n+8 a 3 l l llllq 2+1 load write n+9 x x h x l l x z burst write n+10 a 4 l l lllxd 3 load write n+11 x x l h l x x d 3+1 deselect or stop n+12 x x h x l x x d 4 noop n+13 a 5 l l lllxzload write n+14 a 6 hl llxxzload read n+15 a 7 l l lllxd 5 load write n+16 x x h x l l l q 6 burst write n+17 a 8 hl llxxd 7 load read n+18 x x h x l x x d 7+1 burst read n+19 a 9 l l llllq 8 load write 5 313 tbl 12 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x x x l x x x clock setup valid n+2 x x x xxxlq 0 contents of address a 0 read out 5 313 tbl 13
6.42 10 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges burst write operation (1) burst read operation (1) write operation (1) notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = don?t care; ? = don?t know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x h x l x x x clock setup valid, advance counter n+2 x x h x l x l q 0 address a 0 read out, inc. count n+3 x x h x l x l q 0+1 address a 0+1 read out, inc. count n+4 x x h x l x l q 0+2 address a 0+2 read out, inc. count n+5 a 1 hl llxlq 0+3 address a 0+3 read out, load a 1 n+6 x x h x l x l q 0 address a 0 read out, inc. count n+7 x x h x l x l q 1 address a 1 read out, inc. count n+8 a 2 hl llxlq 1+1 address a 1+1 read out, load a 2 5 313 tbl 14 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup n+1 x x x x l x x x clock setup valid n+2 x x x x l x x d 0 write to address a 0 5 313 tbl 15 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup n+1 x x h x l l x x clock setup valid, inc. count n+2 x x h x l l x d 0 address a 0 write, inc. count n+3 x x h x l l x d 0+1 address a 0+1 write, inc. count n+4 x x h x l l x d 0+2 address a 0+2 write, inc. count n+5 a 1 l l lllxd 0+3 address a 0+3 write, load a 1 n+6 x x h x l l x d 0 address a 0 write, inc. count n+7 x x h x l l x d 1 address a 1 write, inc. count n+8 a 2 l l lllxd 1+1 address a 1+1 write, load a 2 5 313 tbl 16
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 11 read operation with clock enable used (1) write operation with clock enable used (1) notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = don?t care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a 1 h l l l x x x clock valid n+3 x x x x h x l q 0 clock ignored. data q 0 is on the bus. n+4 x x x x h x l q 0 clock ignored. data q 0 is on the bus. n+5 a 2 hl llxlq 0 address a 0 read out (bus trans.) n+6 a 3 hl llxlq 1 address a 1 read out (bus trans.) n+7 a 4 hl llxlq 2 address a 2 read out (bus trans.) 5 313 tbl 17 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup. n+1 x x x x h x x x clock n+1 ignored. n+2 a 1 l l lllxxclock valid. n+3 x x x x h x x x clock ignored. n+4 x x x x h x x x clock ignored. n+5 a 2 l l lllxd 0 write data d 0 n+6 a 3 l l lllxd 1 write data d 1 n+7 a 4 l l lllxd 2 write data d 2 5 313 tbl 18
6.42 12 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges notes: 1. h = high; l = low; x = don?t care; ? = don?t know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 3. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. read operation with chip enable used (1) write operation with chip enable used (1) notes: 1. h = high; l = low; x = don?t care; ? = don?t know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce (2) cen bw x oe i/o (3 ) comments n x x l h l x x ? deselected. n+1 x x l h l x x ? deselected. n+2 a 0 h l l l x x z address and control meet setup. n+3 x x l h l x x z deselected or stop. n+4 a 1 hl llxlq 0 address a 0 read out. load a 1 . n+5 x x l h l x x z deselected or stop. n+6 x x l h l x l q 1 address a 1 read out. deselected. n+7 a 2 h l l l x x z address and control meet setup. n+8 x x l h l x x z deselected or stop. n+9 x x l h l x l q 2 address a 2 read out. deselected. 5 313 tbl 19 cycle address r/ w adv /ld ce (2) cen bw x oe i/o comments n x x l h l x x ? deselected. n+1 x x l h l x x ? deselected. n+2 a 0 l l l l l x z address and control meet setup. n+3 x x l h l x x z deselected or stop. n+4 a 1 l l lllxd 0 address d 0 write in. load a 1 . n+5 x x l h l x x z deselected or stop. n+6 x x l h l x x d 1 address d 1 write in. deselected. n+7 a 2 l l l l l x z address and control meet setup. n+8 x x l h l x x z deselected or stop. n+9 x x l h l x x d 2 address d 2 write in. deselected. 5 313 tbl 20
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 13 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 2.5v5%) figure 2. lumped capacitive load, typical derating ac test conditions dc electrical characteristics over the operating temperature and supply voltage range (1) (v dd = 2.5v5%) figure 1. ac test load ac test load note: 1. the lbo, tms, tdi, tck and trst pins will be internally pulled to v dd , and the zz pin will be internally pulled to v ss if they are not actively driven in the application. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f=0 means no input lines are changing. 3. for i/os v hd = v ddq ? 0.2v, v ld = 0.2v. for other inputs v hd = v dd ? 0.2v, v ld = 0.2v. symbol parameter test conditions min. max. unit |i li | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i li | lbo , jtag and zz input leakage current (1) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current v out = 0v to v ddq , device deselected ___ 5a v ol output low voltage i ol = +6ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -6ma, v dd = min. 2.0 ___ v 5313 tbl 21 input pulse levels input rise/fall times input timing reference levels output timing reference levels ac test load 0 to 2.5v 2ns (v ddq /2) (v ddq /2) see figure 1 5313 tbl 23 v ddq /2 50 i/o z 0 = 50 5313 drw 04 1 2 3 4 20 30 50 100 200 t cd (ty pi cal , ns ) capaci t ance (pf ) 80 5 6 ? ? ? ? ? 5313 dr 05 symbol parameter test conditions 200mhz 166mhz 150mhz 133mhz 100mhz unit com'l ind com'l ind com'l ind com'l ind com'l ind i dd operating power supply current device selected, outputs open, adv/ ld = x, v dd = max., v in > v ih or < v il , f = f max (2) 275 295 245 265 215 235 195 215 175 195 ma i sb1 cmos standby power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = 0 (2,3) 40 60 40 60 40 60 40 60 40 60 ma i sb2 clock running power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = f max (2.3) 80 100 70 90 60 80 50 70 45 65 ma i sb3 idle power supply current device selected, outputs open, cen > v ih , v dd = max., v in > v hd or < v ld , f = f max (2,3) 60 80 60 80 60 80 60 80 60 80 ma i zz full sleep mode supply current device selected, outputs open, cen < v ih , v dd = max., v in > v hd or < v ld , f = f max (2,3) ,zz > v hd 40 60 40 60 40 60 40 60 40 60 ma 5313 tbl 22
6.42 14 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges ac electrical characteristics (v dd = 2.5v +/-5%, commercial and industrial temperature ranges) notes: 1. tf = 1/t cyc . 2. measured as high above 0.6v ddq and low below 0.4v ddq . 3. transition is measured 200mv from steady-state. 4. these parameters are guaranteed with the ac load (figure 1) by device characterization. they are not production tested. 5. to avoid bus contention, the output buffers are designed such that t chz (device turn-off) is faster than t clz (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because t clz is a min. parameter that is worse case at totally different test conditions (0 deg. c, 2.625v) than t chz , which is a max. parameter (worse case at 70 deg. c, 2.375v). 200mhz 166mhz 150mhz 133mhz 100mhz symbol parameter min. max. min. max. min. max. min. max. min. max. unit t cyc clock cycle time 5 ____ 6 ____ 6.7 ____ 7.5 ____ 10 ____ ns t f (1) clock frequency ____ 200 ____ 166 ____ 150 ____ 133 ____ 100 mhz t ch (2) clock high pulse width 1.8 ____ 1.8 ____ 2.0 ____ 2.2 ____ 3.2 ____ ns t cl (2) clock low pulse width 1.8 ____ 1.8 ____ 2.0 ____ 2.2 ____ 3.2 ____ ns output parameters t cd clock high to valid data ____ 3.2 ____ 3.5 ____ 3.8 ____ 4.2 ____ 5ns t cdc clock high to data change 1.0 ____ 1.0 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns t clz (3,4,5) clock high to output active 1.0 ____ 1.0 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns t chz (3,4,5) clock high to data high-z 1.0 3 1.0 3 1.5 3 1.5 3 1.5 3.3 ns t oe output enable access time ____ 3.2 ____ 3.5 ____ 3.8 ____ 4.2 ____ 5ns t olz (3,4) output enable low to data active 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns t ohz (3,4) output enable high to data high-z ____ 3.2 ____ 3.5 ____ 3.8 ____ 4.2 ____ 5ns set up times t se clock enable setup time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns t sa address setup time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns t sd data in setup time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns t sw read/write (r/ w ) setup time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns t sadv advance/load (adv/ ld ) setup time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns t sc chip enable/select setup time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns t sb byte write enable ( bw x) setup time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns hold times t he clock enable hold time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t ha address hold time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hw read/write (r/ w ) hold time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hadv advance/load (adv/ ld ) hold time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns t hb byte write enable ( bw x) hold time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns 5313 tbl 24
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 15 timing waveform of read cycle (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . q (a 2 ) represents the first output from the external address a 2 ; q (a 2+1 ) represents the next output data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. adv/ ld ( cen high, eliminates current l-h clock edge) t cd t hadv pipeline read (burst wraps around to initial state) t cdc t clz t chz t cd t cdc r/ w clk cen address oe data out t he t se a1 a2 t ch t cl t cyc t sadv t hw t sw t ha t sa t hc t sc burst pipeline read pipeline read bw 1 - bw 4 5313 drw 06 ce 1 , ce 2 (2) q(a 2+3 ) q(a 2 ) q(a 2+2 ) q(a 2+2 ) q(a 2+1 ) q(a 2 ) q(a 1 )
6.42 16 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges notes: 1. d (a 1 ) represents the first input to the external address a 1 . d (a 2 ) represents the first input to the external address a 2 ; d (a 2+1 ) represents the next input data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. 5. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of write cycles (1,2,3,4,5) t he t se r / w a 1 a 2 clk c e n adv / l d address o e data in t hd t sd t ch t cl t cyc t hadv t sadv t hw t sw t ha t sa t hc t sc burst pipeline write pipeline write pipeline write t hb t sb (burst wraps around to initial state) t hd t sd ( cen high, eliminates current l-h clock edge) (2) d( a2+2 ) d( a2+3 ) d(a 1 ) d(a 2 ) d(a 2 ) 5313 drw 07 b w 1 - b w 4 c e 1, c e 2 d(a 2+1 )
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 17 notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of combined read and write cycles (1,2,3) t he t se r/ w a 1 a 2 clk cen adv/ ld address ce 1 , ce 2 (2) bw 1 - bw 4 data out q(a 3 ) q(a 1 ) q(a 6 ) q(a 7 ) t cd read t chz 5313 drw 08 write t clz d(a 2 ) d(a 4 ) t cdc d(a 5 ) write t ch t cl t cyc t hw t sw t ha t sa a 4 a 3 t hc t sc t sd t hd t hadv t sadv a 6 a 7 a 8 a 5 a 9 data in t hb t sb oe read read
6.42 18 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of cen operation (1,2,3,4) t he t se r / w a 1 a 2 clk c e n adv / l d address b w 1 - b w 4 o e data out q(a 3 ) t cd t clz t chz t ch t cl t cyc t hc t sc d(a 2 ) t sd t hd t cdc a 4 a 5 t hadv tsadv t hw t sw t ha t sa a 3 t hb t sb data in q(a 1 ) 5313 drw 09 q(a 1 ) b(a 2 ) c e 1 , c e 2 (2)
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 19 timing waveform of cs operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 3 ) represents the input data to the sram corresponding to address a 3 . 2ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. r/ w a1 clk adv/ l d address o e data out q(a 1 ) t cd t clz t chz t cdc t ch t cl t cyc t hc t sc t sd t hd a 5 a 3 t sb data in t he t se a 2 t ha t sa a 4 t hw t sw t hb c e n t hadv t sadv 5313 drw 10 q(a 2 ) q(a 4 ) d(a 3 ) b w 1 - b w 4 c e 1, c e 2 (2)
6.42 20 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges jtag interface specification tck device inputs (1) / tdi/tms device outputs (2) / tdo trst ( 3) t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch m5313 drw 01 x symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 5 (1) ns t jf jtag clock fall time ____ 5 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 20 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 25 ____ ns t jh jtag hold 25 ____ ns i5313 tbl 01 register name bit size instruction (ir) 4 bypass (byr) 1 jtag identification (jidr) 32 boundary scan (bsr) note (1) i5313 tbl 03 notes: 1. device inputs = all device inputs except tdi, tms and trst . 2. device outputs = all device outputs except tdo. 3. during power up, trst could be driven low or not be used since the jtag circuit resets automatically. trst is an optional jtag reset. note: 1. the boundary scan descriptive language (bsdl) file for this device is available by contacting your local idt sales representative. jtag ac electrical characteristics (1,2,3,4) scan register sizes notes: 1. guaranteed by design. 2. ac test load (fig. 1) on external output signals. 3. refer to ac test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet.
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 21 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . instruction field value description revision number (31:28) 0x2 reserved for version number. idt device id (27:12) 0x220, 0x222 define s idt part number 71t75602 and 71t75802, respectively. idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt. id register indicator bit (bit 0) 1 indicates the presence of an id register. i5313 tbl 02 jtag identification register definitions instruction description opcode extest forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. 0000 sample/preload places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. 0001 device_id loads the jtag id register (jidr) with the vendor id code and places the register between tdi and tdo. 0010 highz places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. 0011 reserved several combinations are reserved. do not use codes other than those identified for extest, sample/preload, device_id, highz, clamp, validate and bypass instructions. 0100 reserved 0101 reserved 0110 reserved 0111 clamp uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. 1000 reserved same as above. 1001 reserved 1010 reserved 1011 reserved 1100 validate automatically loaded into the instruction register whenever the tap controller passes through the capture-ir state. the lower two bits '01' are mand ated by the ieee std. 1149.1 specification. 1101 reserved same as above. 1110 bypass the bypass instruction is used to truncate the boundary scan register as a single bit in length. 1111 i5313 tbl 04 available jtag instructions
6.42 22 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges timing waveform of oe operation (1) note: 1. a read operation is assumed to be in progress. ordering information oe data out t ohz t olz t oe valid 5313 drw 11 100-pin plastic thin quad flatpack (tqfp) tqfp - green 119 ball grid array (bga) bga - green s power xx speed xx package xxxx *200 166 150 133 100 clock frequency in megahertz 5313 drw 12 device type 71t75602 71t75802 512kx36 pipelined zbt sram 1mx18 pipelined zbt sram pf pfg bg bgg x blank i commercial (0c to +70c) industrial (-40c to +85c) blank 8 tube or tray tape and reel x * 200mhz available only for idt71t75802
6.42 idt71t75602, idt71t75802, 512k x 36, 1m x 18, 2.5v synchronous zbt? srams with 2.5v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 1 datasheet document history rev date pages description 0 04/20/00 created new datasheet 1 05/25/00 pg.1,14,15,25 added 166mhz speed grade offering pg. 1,2,14 corrected error in zz sleep mode pg. 23 addbq165 package diagram outline pg. 24 corrected 119bga package diagram outline. pg. 25 corrected topmark on ordering information 2 08/23/01 pg. 1,2,24 removed reference of bq165 package pg. 7 removed page of the 165 bga pin configuration pg. 23 removed page of the 165 bga package diagram outline 3 10/16/01 pg. 6 corrected 3.3v to 2.5v in note 2 10/29/01 pg. 13 improved dc electrical characteristics-parameters improved: icc, isb2, isb3, izz. 4 12/21/01 pg. 4-6 added clarification to jtag pins, allow for nc. added 36m address pin locations. pg. 14 revised 166mhz t cdc (min), t clz (min) and t chz (min) to 1.0ns 5 06/07/02 pg. 1-3,6,13,20,21 added complete jtag functionality. pg. 2,13 added notes for zz pin internal pulldown and zz leakage current. pg. 13,14,24 added 200mhz and 225mhz to dc and ac electrical characteristics. updated supply current for idd, isb1, isb3 and izz. 6 11/19/02 pg.1-24 changed datasheet from advanced information to final release. pg.13 updated dc electrical characteristics temperature and voltage range table. 7 05/23/03 pg.4,5,13,14,24 added i-temp to the datasheet. pg.5 updated 165 bga capacitance table. 8 04/01/04 pg. 1 updated logo with new design. pg. 4,5 clarified ambient and case operating temperatures. pg. 6 updated pin i/o number order for the 119 bga. pg. 23 updated 119bga package diagram drawing. 9 10/01/08 pg. 1,13,14,24 deleted 225mhz part, added 200mhz industrial grade and added green packages. updated the ordering information by removing the ?idt? notation. 10 04/04/12 pg. 2,22 updated text on page 2 last paragraph. added note to ordering information and updated to include tube or tray and tape & reel. . the idt logo is a registered trademark of integrated device technology, inc. all brands or products are the trademarks or regi stered trademarks of their respective owners. zbt ? and zero bus turnaround are trademarks of integrated device technology, inc. and the architecture is supported by micron techn ology and motorola inc. corporate headquarters for sales: for tech support: 6024 silver creek valley rd 800-345-7015 or 408-284-8200 sramhelp@idt.com san jose, ca 95138 fax: 408-284-2775 408-284-4532 www.idt.com

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